1. Field of the Invention
This invention relates generally to electronic comparators and specifically to a circuit for sensing the polarity of a net input current at a current summing node. The invention is particularly well suited for providing an improved apparatus and method for analog-to-digital signal conversion.
2. Description of the Prior Art
The growth of fast computer and microprocessor controlled systems has created considerable demand for low-cost, high-speed analog-to-digital (A/D) converters. Many such converters are known and exploit a variety of algorithms to arrive at the desired digital output signal. Successive approximation A/D conversion is a popular choice in many systems today because it achieves high conversion rates at low cost. Other methods such as tracking (servo) or staircase (ramp) can require up to "2n" clock cycles per conversion, where "n" is the number of bits of resolution, while successive approximation requires only "n+1" clock cycles. In the successive approximation method, a series of known electrical voltages or currents are generated on a trial basis, typically by a digital-to-analog (D/A) converter, and are compared with the analog input signal of unknown value. The first trial compares the analog input to the value of the Most Significant Bit (MSB) or approximately one-half full scale. If the input is greater than the MSB value, the MSB is retained and the converter moves on to trying the next most significant bit, or approximately three-quarters full scale. If the input had been less than the MSB, the logic would have turned the MSB off before going on to the next most significant bit, one-quarter full-scale. This branching continues until each successively smaller bit has been tried, with the entire process taking "n" trials. The digital number best representing the analog input voltage is then available from the input to the D/A converter as a readout. U.S. Pat. No. 3,836,905 issued Sept. 17, 1974, to Charles Cross entitled "Analog-to-Digital Converter" provides a detailed discussion of logic which can be used to implement the successive approximation algorithm discussed above.
Early A/D converters performed a comparison between the analog input voltage and the output voltage from a D/A converter by applying these voltages respectively to a pair of input terminals on a voltage comparator. Later A/D converter designs achieved higher conversion speeds by using the output of a fast current output D/A converter directly at a current summing node. In such converters, higher conversion speed is achieved by eliminating the need for a current-to-voltage converting operational amplifier in the D/A converter which is by far the slowest element in such converters.
One of the problems involved with high speed conversion is the stray capacitance at the summing node. The largest component of this stray capacitance is associated with the output of the D/A converter. To ensure accuracy, it is generally accepted that the voltage at the summing node must settle to within one-half of the Least Significant Bit (LSB) before each of the trial comparisons can be made. Some prior art A/D converters have employed clamping devices such as, for example, Schottky diodes to reduce the voltage swing at the summing node thereby decreasing the effect of stray capacitance at the node. However, the effectiveness of such clamps is limited because of the exponential nature of the discharge rate at the summing node. U.S. Pat. No. 3,811,125 issued to Robert W. Schumann on May 14, 1974, entitled, "Analog-to-Digital Converter" teaches the use of a diode clamp and a clock controlled periodic current to hasten the return of the voltage at the summing node to a predetermined value prior to each trial comparison thereby achieving higher conversion speeds. Additionally, the patent provides a good, general discussion of factors affecting the settling time of the summing node.
Notwithstanding the many prior art improvements of which the above examples are but illustrative, conversion speed in successive approximation-type A/D converters remains a problem. A limitation that all prior art designers of A/D converters labored under was the essentially voltage sensitive nature of all heretofore known comparator circuits. For proper operation, such comparator circuits require that the voltage at the summing node change not insignificantly thereby requiring the stray capacitance to be charged and subsequently discharged. Although those skilled in the art will appreciate that the distinction between a comparator circuit being voltage sensitive or current sensitive is in a sense somewhat philosophical, the apparatus of the present invention will be understood as being predominantly current sensitive.